Conventionally, non-crystalline (amorphous) silicon TFTs (Thin Film Transistors), microcrystalline silicon TFTs, polycrystalline silicon (polysilicon) TFTs, or the like have been used as TFTs for an active matrix substrate in a display device such as a liquid crystal display device and the like.
Amorphous silicon TFTs are suitable for TFTs of a display device that requires a large region because forming an amorphous silicon film is relatively easy. Accordingly, the amorphous silicon TFTs are used in many of active matrix substrates of liquid crystal televisions having a relatively large screen.
In a microcrystalline silicon TFT and a polycrystalline silicon TFT, the mobilities of electrons and holes in a semiconductor layer are high and an on-current is large. Thus, there is an advantage that a pixel capacitance of a liquid crystal display device or the like can be charged within a short switching time. Also, if microcrystalline silicon TFTs and polycrystalline silicon TFTs are used, there is an advantage that a part or all of peripheral circuits such as a driver and the like can also be fabricated in an active matrix substrate.
Manufacturing methods of a polycrystalline silicon TFT are described in Patent Document 1 and Patent Document 2. Patent Document 1 relates to a manufacturing method of a bottom gate type TFT and Patent Document 2 relates to a manufacturing method of a top gate type TFT. FIG. 7 is a cross sectional view showing a manufacturing method of a TFT described in Patent Document 1.
In the manufacturing method of a TFT described in Patent Document 1, initially, a conductive layer is formed on a substrate 110, and then, a gate electrode 131 is formed by patterning the conductive layer using the photolithography. After that, an insulating layer 121 is formed by depositing silicon dioxide or the like by a CVD method. Next, after depositing a silicon layer made of polysilicon or amorphous silicon on the insulating layer 121, a semiconductor layer 132 is formed by patterning the silicon layer using the photolithography. This way, a structure shown in FIG. 7(a) is obtained.
Next, as shown in FIG. 7(b), the structure is irradiated with laser light from a side of the substrate 110 at an oblique angle with respect to a substrate surface. The irradiation angle θ of the laser light with respect to the substrate surface is set to be 10 to 80°. By this laser light irradiation, the semiconductor layer 132 is heated using the gate electrode 131 as a mask and a part of the semiconductor layer 132 is melted. In case of forming a N type MOS, arsine (AsH3), phosphine (PH3), or the like, and in case of forming a P type MOS, diborane (B2H6), phosphorus trichloride (PCl3), boron fluoride (BF3) or the like is introduced as an ambient gas at this time. This way, an impurity in the ambient gas is doped only into the melted part of the semiconductor layer 132, and a low concentration impurity diffusion region 132b is formed as shown in FIG. 7(c).
After this, in the atmosphere where the ambient gas including an impurity is present, a second laser light irradiation using the gate electrode 131 as a mask is performed from a direction normal to the surface of the substrate 110, as shown in FIG. 7(d). By the second irradiation, parts of the semiconductor layer 132 except for the part blocked by the gate electrode 131 are melted. At this time, the impurity in the ambient gas is doped into the melted parts and high concentration impurity diffusion regions 132a of a source region (S) and a drain region (D) are formed, as shown in FIG. 7(e).
In the low concentration impurity diffusion region 132b that was formed by the first laser light irradiation, the part that was not irradiated with the second laser light remains as the low concentration impurity diffusion region 132b. This part becomes a low concentration diffusion drain (LDD: Lightly Doped Drain). The LDD is only formed in one location in the drain region. The part of the semiconductor layer 132 that was not irradiated with either first or second laser light becomes a channel region (C) having no impurity doped therein.
The TFT formed as described above is assumed to be manufacturable with a small number of steps because the LDD, source, and drain are formed in the thin film transistor of the bottom gate structure in a self-aligned manner. Also, a leak current can be decreased because an electric field concentration in the vicinity of a junction of the channel region and the drain region can be reduced by the LDD.